Domino circuits are widely used as memory devices in integrated circuits. Domino circuits operate in one of two distinct phases. In the first phase, called the precharge phase, a node is precharged to a first potential. In the second phase, called the discharge phase, the node is discharged and the signal output from the domino logic circuit represents the state of a memory cell included in the domino circuit. Included in the domino circuit are a precharge transistor and a discharge transistor which control precharging and discharging, respectively.
One prior art domino circuit configuration 10 is depicted in FIG. 1, which illustrates a first domino circuit 12 and a second domino circuit 14. The first domino circuit includes eight memory cells 16 (only one of the eight memory cells is shown), eight discharge transistor pairs 18 (only one of the eight readout transistor pairs is shown) that each include a read enable transistor 20 and a memory cell transistor 22, and a first precharge transistor 24. The second domino circuit includes eight discharge transistors 26 and a second precharge transistor 28.
Also shown in FIG. 1, various digital signals are input or internal to, or output from the domino circuit configuration. In particular, signal rwl0 is a control signal used to enable readout of data from the memory cell 16. Signal rwl0_buf is the signal rwl0 after passing through a first buffer 30. Signal rwl0_buf is input to the gate 32 of the read enable transistor 20, and thus, controls the readout of data from the memory cell.
Signal lblpch_b is a control signal utilized to precharge signal lbl. Signal lblpch_buf_b is signal lblpch_b after passing through a second buffer 36. Signal lblpch_buf_b is input to the gate 38 of a first precharge transistor 24, and thus, signal lblpch_buf_b controls the precharging of the first domino circuit 12 via signal lbl which is input to the drain 40 of the read enable transistor 20 and also the input 42 of a first inverter 44. Signal lbl becomes signal lbl_b after passing through the first inverter. Signal lbl_b is input to the gate 34 of the discharge transistor 26 which turns on when signal lbl_b transitions from “low” or “logic level 0” to “high” or “logic level 1”. Correspondingly, the discharge transistor turns off when signal lbl_b transitions from logic level 1 to logic level 0.
Signal gblpch_b is a control signal utilized to precharge signal gbl which is input to the drain 46 of the discharge transistor 26. Signal gblpch_b becomes signal gbl_b after passing through a third buffer 48. Signal gbl_b is input to the gate 50 of a second precharge transistor 28, and thus, signal gbl_b controls the precharging of the second domino circuit 14 via signal gbl which is output from the second precharge transistor's source 52 and input to the discharge transistor's drain 46. Signal output is the digital signal output from the domino circuit configuration 10.
FIG. 2 is a timing diagram that illustrates the waveform for each of the digital signals and shows the timing relationship between the waveforms. In particular, FIG. 2 shows that Tr_dly1 is the time delay between the rising edges 60 and 62, respectively, of signals rwl0 and rwl0_buf, the time delay between the rising edges 64 and 66, respectively, of signals lblpch_b and lblpch_buf_b, and the time delay between the rising edges 68 and 70, respectively, of signals gblpch_b and gbl_b. Likewise, Tf_dly1 is the time delay between the falling edges 72 and 74, respectively, of signals rwl0 and rwl0_buf, the time delay between the falling edges 76 and 78, respectively, of signals lblpch_b and lblpch_buf_b, and the time delay between the falling edges 80 and 82, respectively, of signals gblpch_b and gbl_b. Tf_dly_lbl is the time delay between the rising edge 66 of signal lblpch_buf_b and the falling edge 84 of signal lbl. Likewise, Tr_dly_lbl is the time delay between the falling edge 78 of signal lblpch_buf_b and the rising edge 86 of signal lbl. Tr_dly2 is the time delay between the falling edge 84 of signal lbl and the rising edge 88 of signal lbl_b. Tf_dly2 is the time delay between the rising edge 86 of signal lbl and the falling edge 90 of signal lbl_b. Tf_dly_rwl02gbl is the time delay between the rising edges 60 and 88, respectively, of signals rwl0 and lbl_b. Tr_dly_lblpch_b2gbl is the time delay between the falling edges 72 and 90, respectively, of signals rwl0 and lbl_b.
Referring additionally to FIG. 1, the domino circuit configuration 10 of FIG. 1 operates as follows. When signal rwl0 is at logic level 1, the state of the memory cell 16 can be read when signal lblpch_b is at logic level 1. Also, the first precharge transistor 24 turns on when signal lblpch_buf_b transitions from logic level 1 to logic level 0, and turns off when signal lblpch_buf_b transitions from logic level 0 to logic level 1. In contrast, the second precharge transistor 28 turns on when signal gbl_b transitions from logic level 1 to logic level 0 and turns off when signal gbl_b transitions from logic level 0 to logic level 1. The discharge transistor 26 turns on when signal lbl_b transitions from logic level 0 to logic level 1 and turns off when signal lbl_b transitions from logic level 1 to logic level 0.
However, because Tr_dly1, the time delay from the trailing edge 80 of signal gblpch_b to the trailing edge 82 of signal gbl_b, is shorter than Tr_dly_blpch_b2gbl, the time delay from the trailing edge 76 of signal lblpch_b to the trailing edge 90 of signal lbl_b, both the precharge transistor 28 and the discharge transistor 26 are on simultaneously as shown in FIG. 2. As a result, direct current flows through both the second precharge transistor and the discharge transistor in the circuit depicted in FIG. 1 as indicated by the bold arrow 92. The flow of direct current through both the second precharge transistor and the discharge transistor results in power inefficiencies. Thus, there is a need for a domino circuit configuration which prevents the flow of direct current between precharge and discharge transistors.